The present invention relates to a data processing system, and more particularly, to a multi-level data processing system suitable for signal synthetic processing.
Many memory devices for storing data in a binary system are widely known in the art; thus, it is common to process and store various types of data with a digital computer. A central processing unit (CPU), also called a processor, is customarily used to read and execute a command; thus, it is a considerably important component in a digital computer. FIG. 1 is a typical schematic diagram showing the interconnection of a central processing unit 11. The central processing unit essentially includes a control unit 111, an arithmetic logical unit 112 and a register unit 113. The control unit 111 is used to control the operation of the central processing unit 11. The arithmetic logical unit 112 is used to conduct the arithmetic calculation of the computer. And the register unit 113 is used to be a memory unit of the central processing unit 11. Owing to the interconnection of the control unit 111, the arithmetic logical unit 112 and the register unit 113, the data transmissions among such units are proceeded so as to perform the overall data processing.
However, in the circuit device for storing and processing data in a binary system, the number of storage cell is usually not sufficient, because the data stored in a binary system having two level signals representing 0 or 1, are considerable. Especially, the large amounts of storage cells are required for storing the increasingly utilized sound signals. Furthermore, using the traditional central processing unit to process sound signals still has too many difficulties to cope with.
Because storing analog signals requires less memory space than storing digital data, the use of analog memory for storing digital data as multi-level voltage signals has been attempt ed to overcome the problem described.
An object of the present invention is to provide an improved data processing system by using a multi-level memory cell.
Another object of the present invention is to provide a data processing system for storing and processing sound signals.
The present system comprises a control command storage device, a data storage device, an address pointer, a multi-level signal decoder and a data processing unit. The control command storage device is used to store a control command in an n-level form, wherein n is an integer and at least 2. The data storage device is used to store the data to be processed in an m-level data form, wherein m is an integer and greater than 2. Preferably, both m and n are greater than 2. The address pointer is electrically connected to the control command storage device and the data storage device for pointing toward a first address of the control command storage device and a second address of the data storage device. The multi-level signal decoder is electrically connected to the control command storage device for decoding a control command stored in an n-level data form and read from the first address of the control command storage device, thereby delivering a control signal representing the meaning of the corresponding control command. The data processing unit is electrically connected to the multi-level signal decoder and the data storage device for processing data stored in an m-level data form and read from the second address of the data storage device, thereby delivering an output signal.
Preferably, the control command storage device is a multi-level memory cell. However, the control command storage device is a digital memory cell such as a dynamic random access memory (DRAM) when n is equal to 2.
The address pointer preferably includes a column address device and a row address device.
Preferably, the multi-level decoder comprises a plurality of level comparators. The number of level comparators depends on the number of level signals to be decoded.
The data processing unit comprises a multi-level data register and a multi-level data processor. The multi-level data register is electrically connected to the data storage device for storing data in an m-level data form. The multi-level data processor is electrically connected to the multi-level data register and the multi-level signal decoder for processing the data stored in the multi-level data register in an m-level data form in response to the command signal and delivering an output signal. Owing to the difference of the control signals, the processing of the multi-level data processor includes a variety of operations, for example adding, subtracting, zeroing and maintaining unchanged. When the processing relates to an operation such as zeroing or maintaining unchanged, the multi-level data processor delivers an analog address signal and at this situation the multi-level data processor further includes an analog-to-digital converter and a program counter. The analog-to-digital converter is electrically connected to the multi-level data processor for converting the analog address signal to a digital address signal, and then the digital address signal is delivered to a program counter. The program counter is electrically connected to the analog-to-digital converter and the address pointer for delivering a counting signal to the address pointer in response to the digital address signal, and it further controls the address pointer to point toward the corresponding addresses of the control command storage device and the data storage device.
In accordance with an aspect of the present invention, the control command storage device is a tri-level memory cell, which stores the operational control commands representing xe2x80x9c0xe2x80x9d, xe2x80x9c+xe2x80x9d and xe2x80x9cxe2x88x92xe2x80x9d in small, medium and large voltage-level signal forms, respectively. Preferably, the multi-level decoder comprises two comparators. The first voltage comparator is electrically connected to the tri-level memory cell and a first fixed reference voltage V0 for delivering a high-level voltage signal representing one of xe2x80x9c0xe2x80x9d, xe2x80x9c+xe2x80x9d and xe2x80x9cxe2x88x92xe2x80x9d operational control commands such as xe2x80x9c0xe2x80x9d, when the voltage-level signal read from the tri-level memory cell is a small voltage-level signal and smaller than the first fixed reference voltage V0. The second voltage comparator is electrically connected to the tri-level memory cell and a second fixed reference voltage V1 for delivering a high-level voltage signal representing one of xe2x80x9c0xe2x80x9d, xe2x80x9c+xe2x80x9d and xe2x80x9cxe2x88x92xe2x80x9d operational control commands such as xe2x80x9c+xe2x80x9d, when the voltage-level signal read from the tri-level memory cell is a medium voltage-level signal and smaller than said second fixed reference voltage V1. On the contrary, it delivers a low-level voltage signal representing one of xe2x80x9c0xe2x80x9d, xe2x80x9c+xe2x80x9d and xe2x80x9cxe2x88x92xe2x80x9d operational control commands such as xe2x80x9cxe2x88x92xe2x80x9d, when the voltage-level signal read from said tri-level memory cell is a large voltage-level signal and greater than the second fixed reference voltage V1. The data storage device is used to store an m-level voltage signal representing amplitude difference of the output signal. Certainly, under the similar configuration, the data processing system can be varied for storing the operational control commands representing xe2x80x9cNxe2x80x9d (i.e. maintaining unchanged), xe2x80x9c+xe2x80x9d and xe2x80x9cxe2x88x92xe2x80x9d.
In accordance with another aspect of the present invention, the control command storage device is a quartet-level memory cell for storing the operational control commands representing xe2x80x9cNxe2x80x9d, xe2x80x9c+xe2x80x9d, xe2x80x9cxe2x88x92xe2x80x9d, and xe2x80x9c0xe2x80x9d in four voltage-level signal forms. Preferably, the multi-level decoder comprises three comparators. The first voltage comparator is electrically connected to the quartet-level memory cell and a first fixed reference voltage V0 for delivering a high-level voltage signal representing one of xe2x80x9cNxe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c+xe2x80x9d and xe2x80x9cxe2x88x92xe2x80x9d operational control commands such as xe2x80x9cNxe2x80x9d, when the voltage-level signal read from the quartet-level memory cell is smaller than the first fixed reference voltage V0. The second voltage comparator is electrically connected to the quartet-level memory cell and a second fixed reference voltage V1 for delivering a high-level voltage signal representing one of xe2x80x9cNxe2x80x9d, xe2x80x9c0xe2x80x9d, and xe2x80x9cxe2x88x92xe2x80x9d operational control commands such as xe2x80x9c+xe2x80x9d, when the voltage-level signal read from the quartet-level memory cell is greater than the first fixed reference voltage V0 and smaller than the second fixed reference voltage V1. The third voltage comparator is electrically connected to the quartet-level memory cell and a third fixed reference voltage V2 for delivering a high-level voltage signal representing one of xe2x80x9cNxe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c+xe2x80x9d and xe2x80x9cxe2x88x92xe2x80x9d operational control commands such as xe2x80x9cxe2x88x92xe2x80x9d, when the voltage-level signal read from the quartet-level memory cell is greater than the first second reference voltage and smaller than the third fixed reference voltage V2. On the contrary, it delivers a low-level voltage signal representing xe2x80x9c0xe2x80x9d operational control command when the voltage-level signal read from the quartet-level memory cell is greater than the third fixed reference voltage V2.